Raid-6 data storage device and data processing system including the same

ABSTRACT

A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2016-0013549 filed on Feb. 3, 2016, the disclosure of which isincorporated herein by reference in its entirety.

BACKGROUND

1. Field

Apparatuses consistent with example embodiments relate to a redundantarray of inexpensive/independent disk (RAID)-6 data storage device and adata storage system including the same.

2. Description of Related Art

In the field of computer storage, RAID is a data storage virtualizationtechnology that combines multiple physical disk drive components into asingle logical unit for the purposes of data redundancy and/orperformance improvement. Data is distributed across the physical diskdrive components in one among several ways referred to as RAID levelsdepending on the level of redundancy and performance.

Standard RAID levels include RAID 0 through RAID 6. RAID 6 consists ofblock-level striping with double distributed parity. Double parityprovides fault tolerance up to two failed drives.

While a read operation is being performed in a RAID 6 data systemincluding data storage devices, an error correction code (ECC) decoderof the RAID 6 data system performs ECC decoding on data that has beenread from one among the data storage devices. When uncorrectable erroroccurs during the ECC decoding, a RAID controller included in the datastorage device reads data from the other data storage devices andrecovers the uncorrectable error using the data. Such error recoverytakes a lot of time. Therefore, an efficient error recovery method isdesired.

SUMMARY

According to example embodiments, a data storage device includes astorage medium configured to store data blocks included in a stripe set,and a controller connected to the storage medium and configured todecode a first data block disposed in a column among the data blocks,during a read operation of the first data block, and read first groupdata blocks disposed in the column among the data blocks, based on aread failure of the first data block.

According to example embodiments, a data storage device includes astorage medium configured to store data blocks included in a stripe set,according to redundant array of inexpensive/independent disk (RAID) 6,and a controller connected to the storage medium and configured todecode a first data block disposed in a column among the data blocks,during a read operation of the first data block, and read second datablocks disposed in the column other than the first data block among thedata blocks, based on a read failure of the first data block.

According to example embodiments, a data processing system includes adata storage device, and a host connected to the data storage device.The data storage device includes a storage medium configured to storedata blocks included in a stripe set, according to redundant array ofinexpensive/independent disk (RAID) 6, and a controller connected to thestorage medium and configured to decode a first data block disposed in acolumn among the data blocks, during a read operation of the first datablock, read second data blocks disposed in the column other than thefirst data block among the data blocks, based on a read failure of thefirst data block, recover the first data block, using the read seconddata blocks, and transmit the recovered first data block to the host.

According to example embodiments, a data storage device includes astorage medium configured to store data blocks, and a controllerconnected to the storage medium and configured to read and decode afirst data block disposed in a column among the data blocks, read anddecode second data blocks disposed in the column other than the firstdata block among the data blocks, based on a read failure of the firstdata block, and recover the first data block based on the decoded seconddata blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a data processing system according toexample embodiments.

FIG. 2 is a diagram of a structure of a redundant array ofinexpensive/independent disk (RAID)-6 stripe set according to exampleembodiments.

FIG. 3 is a block diagram of a flash memory controller illustrated inFIG. 1.

FIG. 4A is a conceptual diagram of a first recovery mode for a failurein reading a single data stripe according to example embodiments.

FIG. 4B is a conceptual diagram of a first recovery mode for a failurein reading a single data stripe and a failure in reading a Q-paritystripe according to example embodiments.

FIG. 5 is a conceptual diagram of a second recovery mode for a failurein reading a single data stripe and a failure in reading a P-paritystripe according to example embodiments.

FIG. 6 is a conceptual diagram of a third recovery mode for a failure inreading two data stripes according to example embodiments.

FIG. 7 is a diagram of storing of a stripe set according to exampleembodiments.

FIG. 8 is a diagram of storing of a stripe set according to exampleembodiments.

FIGS. 9 and 10 are flowcharts of an operation of a data storage deviceillustrated in FIG. 1 according to example embodiments.

FIG. 11 is a flowchart of an operation of the data storage deviceillustrated in FIG. 1 according to example embodiments.

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

As used herein, a data block is a minimum unit on which decoding (e.g.,error correction code (ECC) decoding) is performed and is called an ECCsector.

FIG. 1 is a block diagram of a data processing system 100 according toexample embodiments. The data processing system 100 includes a host 200and a data storage device 300 that may communicate signals with the host200 through an interface 110. The data processing system 100 may be amemory system. The data processing system 100 may be implemented as apersonal computer (PC), a workstation, a data center, an internet datacenter (IDC), a direct attached storage (DAS), a storage area network(SAN), a network attached storage (NAS), or a mobile computing device,but example embodiments are not restricted to these examples. The dataprocessing system 100 may be a smart car or an automotive system. Themobile computing device may be a laptop computer, a smart phone, atablet PC, a personal digital assistant (PDA), an enterprise digitalassistant (EDA), a mobile internet device (MID), a wearable computer, aninternet of things (IoT) device, an internet of everything (IoE) device,or a drone.

The interface 110 may be implemented as a serial advanced technologyattachment (SATA) interface, a SATA express (SATAe) interface, a SAS(serial attached small computer system interface (SCSI)), a peripheralcomponent interconnect express (PCIe) interface, a non-volatile memoryexpress (NVMe) interface, an advanced host controller interface (AHCI),or a multimedia card (MMC) interface, but example embodiments are notrestricted to these examples. The interface 110 may transmit electricalsignals or optical signals.

The host 200 may control a data processing operation (e.g., a write orread operation) of the data storage device 300 through the interface110. The host 200 may refer to a host controller. The host 200 may beimplemented as an integrated circuit (IC), a motherboard, a system onchip (SoC), an application processor (AP), a mobile AP, a web server, adata server, a database server, or an engine control unit (ECU), butexample embodiments are not restricted to these examples.

The data storage device 300 includes a controller 310, a dynamic randomaccess memory (DRAM) 360, and a storage medium 400. For example, thedata storage device 300 may have redundant array ofinexpensive/independent disk (RAID)-6 architecture.

The data storage device 300 may be implemented as a flash-based memorydevice, but example embodiments are not restricted thereto. For example,the data storage device 300 may be implemented as a solid-state drive orsolid-state disk (SSD), an embedded SSD (eSSD), a universal flashstorage (UFS), an MMC, an embedded MMC (eMMC), or a managed NAND, butexample embodiments are not restricted to these examples. Theflash-based memory device may be a NAND-type flash memory device or aNOR-type flash memory device. The data storage device 300 may refer to adatabase. Alternatively, the data storage device 300 may be implementedas a hard disk drive (HDD), a phase-change random access memory (PRAM)device, a magnetoresistive RAM (MRAM) device, a spin-transfer torqueMRAM (STT-MRAM) device, a ferroelectric RAM (FRAM) device, or aresistive RAM (RRAM) device, but example embodiments are not restrictedto these examples.

The controller 310 may control transfer or process of signals among thehost 200, the DRAM 360, and the storage medium 400. The controller 310may be implemented as an IC or a SoC, and may be called an SSDcontroller or a RAID-6 controller. The controller 310 includes atransmission medium 315, a central processing unit (CPU) 320, aninternal memory 325, a read only memory (ROM) 330, a host interface 335,a buffer controller 340, a direct memory access (DMA) controller 345,and a storage medium controller 350.

The transmission medium 315 may be transmission lines or a bus. When thetransmission medium 315 is a bus, the bus may be implemented as anadvanced microcontroller bus architecture (AMBA), an advancedhigh-performance bus (AHB), an advanced peripheral bus (APB), anadvanced extensible interface (AXI), an advanced system bus (ASB), AXIcoherency extensions (ACE), or a combination thereof, but exampleembodiments are not restricted to these examples.

The CPU 320 may control the controller 310. The CPU 320 may control theinternal memory 325, the ROM 330, the host interface 335, the buffercontroller 340, the DMA controller 345, and/or the storage mediumcontroller 350 through the transmission medium 315. The CPU 320 mayinclude at least one core.

The internal memory 325 may store a ROM code or a flash translationlayer (FTL) code that may be executed by the CPU 330. When the datastorage device 300 is booted, the ROM code may be loaded from the ROM330 to the internal memory 325 and the FTL code may be loaded from thestorage medium 400 to the internal memory 325. The internal memory 325may be implemented as RAM, DRAM, static RAM (SRAM), buffer, buffermemory, cache, or tightly couple memory (TCM), but example embodimentsare not restricted to these examples.

The ROM 330 may store the ROM code. The CPU 320 that executes the ROMcode may initialize the host interface 335, the storage mediumcontroller 350, and the DRAM 360. The CPU 320 may load firmware of thecontroller 310 from the storage medium 400 to the DRAM 360, may load thefirmware from the DRAM 360 to the internal memory 325, and may executethe firmware in the internal memory 325.

The host interface 335 may change the format of signals to betransmitted to the host 200 and may transmit the signals in a changedformat to the host 200 through the interface 110. The host interface 335may also receive signals from the host 200, change the format of thesignals, and transmit the signals in a changed format to the CPU 320and/or the buffer controller 340. The host interface 335 may include atransceiver that transmits and receives signals.

The structure and operations of the host interface 335 may be configuredto be compatible with those of the interface 110. The host interface 335may be SATA interface, SATAe interface, SAS, PCIe interface, NVMeinterface, AHCI, MMC interface, NAND-type flash memory interface, orNOR-type flash memory interface but is not restricted thereto.

The buffer controller 340 may write data to or read data from the DRAM360 according to the control of the CPU 320 or the control of thefirmware executed by the CPU 320. The buffer controller 340 may becalled a controller or a buffer manager that controls the write and readoperations performed on the DRAM 360. The DMA controller 345 maytransmit data from the buffer controller 340 to the storage mediumcontroller 350 or transmit data from the storage medium controller 350to the buffer controller 340.

The storage medium controller 350 may control a data processingoperation (e.g., a write operation or a read operation) with respect tothe storage medium 400 through one among a plurality of channels CH1 andCH2 according to the control of the CPU 320 or the control of thefirmware executed by the CPU 320. The storage medium controller 350 maybe implemented as a SATA interface, a SATAe interface, a SAS, a PCIeinterface, an NVMe interface, an AHCI, an MMC interface, a NAND-typeflash memory interface, or a NOR-type flash memory interface, butexample embodiments are not restricted to these examples.

The storage medium controller 350 includes an ECC encoder/decoder 355.The ECC encoder/decoder 355 may generate an ECC sector to be stored inthe storage medium 400. The ECC sector includes data and an ECC parity.The ECC sector is a unit on which the controller 310 performs ECCdecoding. The ECC encoder/decoder 355 may correct an error in an ECCsector output from the storage medium 400. The ECC encoder/decoder 355may be an ECC engine.

The DRAM 360 may receive and store data output from the host interface335 or data output from the DMA controller 345 or may transmit data tothe buffer controller 340 according to the control of the buffercontroller 340. The DRAM 360 is an example of a volatile memory device.

The DRAM 360 may include a first region that stores a mapping table forlogical address-to-physical address translation with respect to thestorage medium 400 and a second region that functions as a cache. TheFTL code executed by the CPU 320 may perform logical address-to-physicaladdress translation using the mapping table stored in the first region.

When the controller 310 and the DRAM 360 are formed in differentsemiconductor chips, respectively; the controller 310 and the DRAM 360may be implemented in a package-on-package (PoP), a multi-chip package(MCP), or a system-in package (SiP), but example embodiments are notrestricted to these examples. A first semiconductor chip including theDRAM 360 may be stacked above a second semiconductor chip including thecontroller 310 using stack balls.

The storage medium 400 includes a plurality of NVM devices 410-1 through410-8 and 420-1 through 420-8. The NVM devices 410-1 through 410-8 areconnected to the first channel CH1, and the NVM devices 420-1 through420-8 are connected to the second channel CH2. Here, a channel may referto an independent data path. The data path may include transmissionlines that transmit data or control signals. The term “way” may refer toa group of one or more non-volatile memory devices that share onechannel. Accordingly, a plurality of ways may be connected to onechannel. For example, eight ways WAY0 through WAY7 are connected to eachof the channels CH1 and CH2.

Each of the NVM devices 410-1 through 410-8 and 420-1 through 420-8(collectively denoted by NAND) may be implemented as a flash memorydevice, which may include a memory cell array. The memory cell array mayinclude a plurality of memory cells. The memory cell array may include atwo-dimensional (2D) memory cell array or a three-dimensional (3D)memory cell array. Each of the memory cells may be implemented as a 2Dor 3D memory cell.

The 3D memory cell array is monolithically formed in one or morephysical levels of arrays of memory cells having an active area disposedabove a silicon substrate and circuitry associated with the operation ofthose memory cells, whether such associated circuitry is above or withinsuch substrate. The term “monolithic” means that layers of each level ofthe array are directly deposited on the layers of each underlying levelof the array. In example embodiments, the 3D memory cell array includesvertical NAND strings that are vertically oriented such that at leastone memory cell is located over another memory cell. The at least onememory cell may include a charge trap layer. The following patentdocuments, which are hereby incorporated by reference, describe suitableconfigurations for three-dimensional memory cell arrays, in which thethree-dimensional memory cell array is configured as a plurality oflevels, with word lines and/or bit lines shared between levels: U.S.Pat. Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and US Pat.Pub. No. 2011/0233648.

FIG. 2 is a diagram of a structure of a RAID-6 stripe set according toexample embodiments. Referring to FIGS. 1 and 2, the RAID-6 stripe setmay be stored in the storage medium 400, specially, the RAID-6 stripeset may be stored in non-volatile memory devices included in the storagemedium 400. The RAID-6 stripe set is conceptually and logicallyillustrated in FIG. 2.

A single RAID-6 stripe set includes N data stripes D₀ through D_(N−1)and two parity stripes D_(N) and D_(N+1). The stripes D₀ through D_(N+1)may be included or stored in different ways (or semiconductor chips),respectively. Each of the stripes D₀ through D_(N+1) includes aplurality of ECC sectors (e.g., L sectors). An ECC sector includes dataDATA and an ECC parity ECC PARITY. The ECC sector may be a unit on whichECC decoding is performed by the controller 310. Here, N and L areintegers of at least 0.

The data storage device 300 may include the storage medium 400 thatstores all data blocks (or ECC sectors) included in a stripe set and thecontroller 310 connected to the storage medium 400. During a readoperation, the controller 310 may decode a first data block logicallyplaced in a column among the all data blocks stored in the storagemedium 400 and may read other data blocks logically arranged in thecolumn when a read failure occurs in the first data block.

As described above, a stripe set including data blocks may be logicallyor physically stored in the storage medium 400 according to RAID 6. Thestorage medium 400 includes the plurality of the NVM devices 410-1through 410-8 and 420-1 through 420-8. The stripe set includes the datastripes D₀ through D_(N−1), the P-parity stripe D_(N), and the Q-paritystripe D_(N+1). As shown in FIG. 7, the data stripes D₀ through D_(N−1),the P-parity stripe D_(N), and the Q-parity stripe D_(N+1) may berespectively stored in the NVM devices 410-1 through 410-8 and 420-1through 420-8. The NVM devices 410-1 through 410-8 are included in therespective (or different) ways WAY0 through WAY7, and the NVM devices420-1 through 420-8 are included in the respective (or different) waysWAY0 through WAY7.

The parity stripes D_(N) and D_(N+1) may be generated by performingextended Reed-Solomon encoding on the N data stripes D₀ through D_(N−1).A j-th ECC sector P[j] in the P-parity stripe P (=D_(N)) and a j-th ECCsector Q[j] in the Q-parity stripe Q (=D_(N+1)) may be calculated usingEquation 1:

P[j]=D ₀ [j]⊕D ₁ [j]⊕D ₂ [j]⊕ . . . ⊕D _(N−2) [j]⊕D _(N−1) [j]

Q[j]=g ₀

D ₀ [j]⊕g ₁

D ₁ [j]⊕g ₂

D ₂ [j]⊕ . . . ⊕g _(N−2)

D _(N−2) [j]⊕g _(N−1)

D _(N−1) [j],  (1)

where D_(i)(j) (0≦i≦(N−1), 0≦j≦(L−1)) is the j-th ECC sector in the i-thdata stripe, g₀, g₁, g₂, . . . g_(N−2), and g_(N−1) are q-bit symbols ofGalois field GF(2^(q)) and may have a value of g_(k)=α^(k) or a value ofg_(k)=α^(N−1−k) in reverse order, ⊕ is a bitwise XOR operator,

is an operator that extends GF(2^(q)) multiplication to a unit of an ECCsector, and α is primitive element of Galois field GF(2^(q)). Forexample, if p(x) is a primitive polynomial of Galois field GF(2^(q)),then α is a root of p(x). Here, it is assumed that 0≦j≦(L−1), N is anatural number of at least 3, and L is a natural number of at least 4.

When Equation 1 is applied to ECC sectors included in each column, L ECCsectors P[0] through P[L−1] for the P-parity stripe P (=D_(N)) arecalculated. When the L ECC sectors P[0] through P[L−1] are connected toone another, the P-parity stripe P (=D_(N)) including the L ECC sectorsP[0] through P[L−1] may be calculated. Also, when Equation 1 is appliedto ECC sectors included in each column, L ECC sectors Q[0] throughQ[L−1] for the Q-parity stripe Q (=D_(N+1)) are calculated. When the LECC sectors Q[0] through Q[L−1] are connected to one another, theQ-parity stripe Q (=D_(N+1)) including the L ECC sectors Q[0] throughQ[L−1] may be calculated.

When g_(k)=α^(N−1−k) is applied to Equation 1, Equation 1 is rewrittenas Equation 2:

$\begin{matrix}\begin{matrix}{{Q\lbrack j\rbrack} = {{\alpha^{N - 1} \otimes {D_{0}\lbrack j\rbrack}} \oplus {\alpha^{N - 2} \otimes {D_{1}\lbrack j\rbrack}} \oplus}} \\{{{\alpha^{N - 3} \otimes {D_{2}\lbrack j\rbrack}} \oplus \cdots \oplus {\alpha^{1} \otimes {D_{N - 2}\lbrack j\rbrack}} \oplus {\alpha^{0} \otimes {D_{N - 1}\lbrack j\rbrack}}}} \\{= {{\alpha \otimes \left( {{\cdots \left( {{\alpha \otimes \left( {{\alpha \otimes {D_{0}\lbrack j\rbrack}} \oplus {D_{1}\lbrack j\rbrack}} \right)} \oplus {D_{2}\lbrack j\rbrack}} \right)} \oplus \cdots} \right)} \oplus}} \\{{{D_{N - 1}\lbrack j\rbrack}.}}\end{matrix} & (2)\end{matrix}$

FIG. 3 is a block diagram of the storage medium controller 350illustrated in FIG. 1. Referring to FIGS. 1 and 3, the storage mediumcontroller 350 is assumed to be a flash memory controller. The flashmemory controller 350 includes the ECC encoder/decoder 355 and a RAID-6engine 357.

The ECC encoder/decoder 355 may generate an encoded ECC sector, anencoded P-parity ECC sector, and an encoded Q-parity ECC sector for awrite operation to the storage medium 400. The ECC encoder/decoder 355may decode an encoded ECC sector, an encoded P-parity ECC sector, and anencoded Q-parity ECC sector for a read operation from the storage medium400. The RAID-6 engine 357 generates a P-parity ECC sector (PD) and aQ-parity ECC sector (QD) using Equation 1, and transmits the P-parityECC sector and the Q-parity ECC sector to the ECC encoder/decoder 355.

FIG. 4A is a conceptual diagram of a first recovery mode MODE0 for afailure in reading a single data stripe according to exampleembodiments. Referring to FIGS. 2 and 4A, when an uncorrectable errorexists in an ECC sector D₂[0] logically placed in a first column COL1even after ECC decoding is performed on the ECC sector D₂[0], a readfailure occurs with respect to the ECC sector D₂[0]. When the readfailure occurs with respect to the ECC sector D₂[0], the controller 310may recover the ECC sector D₂[0] using the first recovery mode MODE0. Inother words, when a read failure occurs with respect to one ECC sectorD₂[0] that is included in the data stripe D₂, the controller 310 mayrecover the ECC sector D₂[0] using the first recovery mode MODE0.

FIG. 4B is a conceptual diagram of the first recovery mode MODE0 for afailure in reading a single data stripe and a failure in reading aQ-parity stripe according to example embodiments. Referring to FIGS. 2and 4B, when a read failure occurs with respect to two ECC sectors D₂[1]and Q[1] logically arranged in a second column COL2 because anuncorrectable error exists in each of the ECC sectors D₂[1] and Q[1]although ECC decoding has been performed on the ECC sectors D₂[1] andQ[1], the controller 310 may recover the ECC sectors D₂[1] and Q[1]using the first recovery mode MODE0.

In other words, when a read failure occurs with respect to each of thetwo ECC sectors D₂[1] and Q[1], one ECC sector D₂[1] between the two ECCsectors D₂[1] and Q[1] is included in the data stripe D₂, and the otherECC sector Q[1] between the two ECC sectors D₂[1] and Q[1] is includedin the Q-parity stripe D_(N+1), the controller 310 may sequentiallyrecover the ECC sectors D₂[1] and Q[1] using the first recovery modeMODE0.

FIG. 5 is a conceptual diagram of a second recovery mode MODE1 for afailure in reading a single data stripe and a failure in reading aP-parity stripe according to example embodiments. Referring to FIGS. 2and 5, when a read failure occurs with respect to two ECC sectors D₁[2]and P[2] logically arranged in a third column COL3 because anuncorrectable error exists in each of the ECC sectors D₁[2] and P[2]although ECC decoding has been performed on the ECC sectors D₁[2] andP[2], the controller 310 may recover the ECC sectors D₁[2] and P[2]using the second recovery mode MODE1.

In other words, when a read failure occurs with respect to each of thetwo ECC sectors D₁[2] and P[2], one ECC sector D₁[2] between the two ECCsectors D₁[2] and P[2] is included in the data stripe D₁, and the otherECC sector P[2] between the two ECC sectors D₁[2] and P[2] is includedin the P-parity stripe D_(N), the controller 310 may sequentiallyrecover the ECC sectors D₁[2] and P[2] using the second recovery modeMODE1.

FIG. 6 is a conceptual diagram of a third recovery mode MODE2 for afailure in reading two data stripes according to example embodiments.Referring to FIGS. 2 and 6, when a read failure occurs with respect totwo ECC sectors D₁[3] and D₂[3] logically arranged in a fourth columnCOL4 because an uncorrectable error exists in each of the ECC sectorsD₁[3] and D₂[3] although ECC decoding has been performed on the ECCsectors D₁[3] and D₂[3], the controller 310 may recover the ECC sectorsD₁[3] and D₂[3] using the third recovery mode MODE2.

In other words, when a read failure occurs with respect to each of thetwo ECC sectors D₁[3] and D₂[3], and the ECC sectors D₁[3] and D₂[3] arerespectively included in the data stripes D₁ and D₂, the controller 310may recover the ECC sectors D₁[3] and D₂[3] using the third recoverymode MODE2.

FIG. 7 is a diagram of storing of a stripe set according to exampleembodiments. Referring to FIGS. 1 and 7, the data stripes D₀ throughD_(N+1) are respectively stored in the NVM devices 410-1 through 410-8and 420-1 through 420-8, each of which is included in a different wayamong the ways WAY0 through WAY7.

FIG. 8 is a diagram of storing of a stripe set according to exampleembodiments. The ECC sectors D₀[0] through D₀[L−1] included in the firstdata stripe D₀ are respectively stored in the NVM devices 410-1, 420-1,. . . , 410-8, and 420-1 through 420-8, each of which is included in adifferent way among the ways WAY0 through WAY7. In addition, the ECCsectors Q[0] through Q[L−1] included in the Q-parity stripe D_(N+1) arerespectively stored in the NVM devices 410-1, 420-1, . . . , 410-8, and420-1 through 420-8, each of which is included in a different way amongthe ways WAY0 through WAY7.

FIGS. 9 and 10 are flowcharts of an operation of the data storage device300 illustrated in FIG. 1 according to example embodiments. Theoperation of the controller 310 that performs the first recovery modeMODE0 when a read failure occurs in a single data stripe will bedescribed in detail with reference to FIGS. 1, 2, 4A, 9, and 10.

It is assumed that a read failure occurs with respect to only the ECCsector D₁[j] (=D₂[0]=D_(k)[j]) logically included in the first columnCOL1 of the third data stripe D₂. At this time, “i” (0≦i≦(N−1)) is 2,“k” (0≦k≦(N−1)) is 2, and “j” (0≦j≦(L−1)) is 0. The controller 310 mayperform the first recovery mode MODE0.

When a read failure is generated with respect to the ECC sector D₂[0] inoperation S110, the controller 310 provisionally decides to perform adefault recovery mode, i.e., the first recovery mode MODE0 in operationS112. Here, c=0 indicates the first recovery mode MODE0.

The controller 310 reads the ECC sector P[j] (=P[0]), e.g., a P-datablock or P-ECC sector, which is included in the P-parity stripe D_(N)and logically placed in the first column COL1, from the storage medium400 (NAND) in operation S114. The ECC encoder/decoder 355 included inthe flash memory controller 350 may decode the ECC sector P[0] and storethe decoded ECC sector P[0] in the DMA controller 345. Alternatively,the decoded ECC sector P[0] may be stored in the DRAM 360 according tothe control of the buffer controller 340. For convenience′ sake in thedescription, one reference character is used to denote both an encodedECC sector stored in the storage medium 400 and a decoded ECC sector.For example, the reference character D₂[0] is used to denote both theencoded ECC sector and the decoded ECC sector. The encoded ECC sectorD₂[0] may include data and an ECC parity, but the decoded ECC sectorD₂[0] may include only the data.

The ECC encoder/decoder 355 determines whether the decoded ECC sectorP[0] has an uncorrectable error in operation S116. When the decoded ECCsector P[0] does not have an uncorrectable error, a read failure doesnot occur (which corresponds to a case of NO) in operation S116.

The controller 310 initiates an operation for reading the ECC sectorD₀[0], which is included in the first data stripe D₀ and logicallyplaced in the first column COL1, from the storage medium 400 by settingi to 0 in operation S120. Because D₀[0] is not D₂[0] (which correspondsto a case of NO) in operation S122, the controller 310 reads the ECCsector D₀[0], which is included in the first data stripe D₀ andlogically placed in the first column COL1, from the storage medium 400in operation S124. The ECC encoder/decoder 355 may decode the ECC sectorD₀[0] and store the decoded ECC sector D₀[0] in the DMA controller 345.Alternatively, the decoded ECC sector D₀[0] may be stored in the DRAM360 according to the control of the buffer controller 340.

The DMA controller 345 may perform a bitwise XOR operation on thedecoded ECC sector P[0] and the decoded ECC sector D₀[0] and may storethe XOR operation result as first destination data. At this time, theDMA controller 345 may include a register that stores the decoded ECCsector P[0], the decoded ECC sector D₀[0], and the first destinationdata. Alternatively, the DMA controller 345 may read the decoded ECCsector P[0] and the decoded ECC sector D₀[0] from the DRAM 360, performa bitwise XOR operation on the decoded ECC sectors P[0] and D₀[0], andstore the XOR operation result in the DRAM 360 as the first destinationdata.

Because a read failure does not occur with respect to the ECC sectorD₀[0] (which corresponds to a case of NO) in operation S126, thecontroller 310 may perform operation S132. Because D₀[0] is not the ECCsector D_(N−1)[0] included in last data stripe D_(N−1) among the datastripes D₀ through D_(N−1) in operation S132, the controller 310 returnsto the operation S122. The controller 310 initiates an operation forreading the ECC sector D₁[0], which is placed in the first column COL1in the second data stripe D₁, from the storage medium 400 in operationS122. Because D₁[0] is not D₂[0] (which corresponds to a case of NO) inoperation S122, the controller 310 reads the ECC sector D₁[0], which isincluded in the second data stripe D₁ and logically placed in the firstcolumn COL1, from the storage medium 400 in operation S124. The ECCencoder/decoder 355 may decode the ECC sector D₁[0] and store thedecoded ECC sector D₁[0] in the DMA controller 345. Alternatively, thedecoded ECC sector D₁[0] may be stored in the DRAM 360 according to thecontrol of the buffer controller 340.

The DMA controller 345 may perform a bitwise XOR operation on the firstdestination data and the decoded ECC sector D₁[0] and may store the XORoperation result in its register as second destination data.Alternatively, the DMA controller 345 may read the first destinationdata and the decoded ECC sector D₁[0] from the DRAM 360, perform abitwise XOR operation on the first destination data and the decoded ECCsector D₁[0], and store the XOR operation result in the DRAM 360 as thesecond destination data.

Because a read failure does not occur with respect to the ECC sectorD₁[0] (which corresponds to a case of NO) in operation S126, thecontroller 310 may perform operation S132. Because D₁[0] is not the ECCsector D_(N−1)[0] in operation S132, the controller 310 returns to theoperation S122. The controller 310 initiates an operation for readingthe ECC sector D₂[0] placed in the first column COL1 from the storagemedium 400 in operation S122. Because D₂[0] is D₂[0] (which correspondsto a case of YES) in operation S122, the controller 310 determineswhether D₂[0] is D_(N−1)[0] in operation S132. In other words, thecontroller 310 determines whether the currently-read ECC sector D₂[0] isthe first ECC sector in the last data stripe D_(N−1) among the datastripes D₀ through D_(N−1) in operation S132.

The controller 310 performs operations S122 through S132 on the ECCsectors D₃[0] through D_(N−1)[0]. After operation S126 is performed onthe first ECC sector D_(N−1)[0] in the last data stripe D_(N−1) amongthe data stripes D₀ through D_(N−1), the controller 310 determineswhether a current recovery mode is the first recovery mode MODE0 inoperation S134. Because the current recovery mode is the first recoverymode MODE0, the controller 310 performs the first recovery mode MODE0according to RAID 6 in operation S142.

The controller 310 may recover the ECC sector D₂[0] using Equation 3:

D ₂[0]=P[0]⊕D ₀[0]⊕D ₁[0]⊕D ₃[0]⊕ . . . ⊕D _(N−2)[0]⊕D _(N−1)[0]  (3)

As described above, when a read failure occurs at the first ECC sectorD₂[0] in the third data stripe D₂, the controller 310 does not read thewhole stripe set but reads only the ECC sectors P[0], D₀[0], D₁[0], andD₃[0] through D_(N−1)[0] included in the first column COL1 that includesthe ECC sector D₂[0] to recover the ECC sector D₂[0]. Accordingly, ascompared to a conventional data storage device that transmits the wholestripe set from a storage medium to a controller, the amount of datatransmitted from the storage medium 400 to the controller 310 isreduced.

The operation of the controller 310 that performs the first recoverymode MODE0 when a read failure occurs in one data stripe D₂ and in theQ-parity stripe D_(N+1) will be described in detail with reference toFIGS. 1, 2, 4B, 9, and 10. It is assumed that a read failure occurs atthe second ECC sector D₂[1] in the third data stripe D₂.

The controller 310 determines whether a current recovery mode is thefirst recovery mode MODE0 in operation S134 in FIG. 10. When the currentrecovery mode is the first recovery mode MODE0 (i.e., in case of YES) inoperation 134, the controller 310 recovers the ECC sector D₂[1] usingthe ECC sectors P[1], D₀[1], D₁[1], and D₃[1] through D_(N−1)[1] withoutreading the second ECC sector Q[1] in the Q-parity stripe D_(N+1).

The operation of the controller 310 that performs the second recoverymode MODE1 when a read failure occurs in one data stripe and in theP-parity stripe D_(N) will be described in detail with reference toFIGS. 1, 2, 5, 9, and 10. It is assumed that a read failure occurs inthe ECC sector D_(i)[j](=D₁[2]=D_(k)[j]) included in the third columnCOL3 and in the ECC sector P[2] included in the third column COL3 in theP-parity stripe D_(N). At this time, “i” is 1, “k” is 1, and “j” is 2.The controller 310 may perform the second recovery mode MODE1.

When a read failure occurs in the ECC sector D₁[2] in operation S110,the controller 310 provisionally decides to perform the first recoverymode MODE0 in operation S112. Here, c=0 indicates the first recoverymode MODE0.

The controller 310 reads the ECC sector P[j] (=P[2]), which is includedin the P-parity stripe D_(N) and placed in the third column COL3, fromthe storage medium 400 in operation S114. The ECC encoder/decoder 355may decode the ECC sector P[2] and store the decoded ECC sector P[2] inthe DMA controller 345. Alternatively, the decoded ECC sector P[2] maybe stored in the DRAM 360 according to the control of the buffercontroller 340.

The ECC encoder/decoder 355 determines whether the decoded ECC sectorP[2] has an uncorrectable error in operation S116. Because the decodedECC sector P[2] has an uncorrectable error, a read failure occurs (whichcorresponds to a case of YES) in operation S116. The controller 310determines to perform the second recovery mode MODE1 in operation S118.Accordingly, “c” is changed to 1 in operation S118.

The controller 310 initiates an operation for reading the ECC sectorD₀[2], which is placed in the first row in the third column COL3, fromthe storage medium 400 by setting i to 0 in operation S120. BecauseD₀[2] is not D₁[2] (which corresponds to a case of NO) in operationS122, the controller 310 reads the ECC sector D₀[2] from the storagemedium 400 in operation S124. The ECC encoder/decoder 355 may decode theECC sector D₀[2] and store the decoded ECC sector D₀[2] in the DMAcontroller 345 or the DRAM 360.

Because a read failure does not occur with respect to the ECC sectorD₀[2] (which corresponds to a case of NO) in operation S126, thecontroller 310 may perform operation S132. Because D₀[2] is not the ECCsector D_(N−1)[2] included in last data stripe D_(N−1) among the datastripes D₀ through D_(N−1) in operation S132, the controller 310 returnsto the operation S122. The controller 310 initiates an operation forreading the ECC sector D₁[2] placed in the third column COL3 from thestorage medium 400 in operation S122. Because D₁[2] is D₁[2] (whichcorresponds to a case of YES) in operation S122, the controller 310performs operation S132.

Because D₁[2] is not D_(N−1)[2], the controller 310 reads the ECC sectorD₂[2] from the storage medium 400 in operation S124. The ECCencoder/decoder 355 may decode the ECC sector D₂[2] and store thedecoded ECC sector D₂[2] in the DMA controller 345 or the DRAM 360.

Because a read failure does not occur with respect to the ECC sectorD₂[2] (which corresponds to a case of NO) in operation S126, thecontroller 310 initiates an operation for reading the ECC sector D₃[2]from the storage medium 400 in operation S122.

The controller 310 performs operations S122 through S132 on the ECCsectors D₃[2] through D_(N−1)[2]. After operation S126 is performed onthe third ECC sector D_(N−1)[2] in the last data stripe D_(N−1) amongthe data stripes D₀ through D_(N−1), the controller 310 may determinewhether a current recovery mode is the first recovery mode MODE0 inoperation S134. Because the current recovery mode is the second recoverymode MODE1 (which corresponds to a case of NO in operation S134), thecontroller 310 reads the third ECC sector Q[2] in the Q-parity stripeD_(N+1) in operation S136.

The controller 310 determines whether a read failure occurs with respectto the third ECC sector Q[2] in operation S140. Because a read failuredoes not occur with respect to the third ECC sector Q[2] (whichcorresponds to a case of NO in operation S140), the controller 310determines whether the current recovery mode is the second recovery modeMODE1 in operation S144. Because c=1 in operation S118, the currentrecovery mode is the second recovery mode MODE1 (which corresponds to acase of YES in operation S144). Accordingly, the controller 310 performsthe second recovery mode MODE1 in operation S146. When a read failuredoes occur with respect to the third ECC sector Q[2] (which correspondsto a case of YES in operation S140), the controller 310 determines thatthere is a RAID-6 recovery failure in operation S138.

Because the third ECC sector Q[2] in the Q-parity stripe D_(N+1) doesnot have an uncorrectable error in the second recovery mode MODE1, thecontroller 310 may recover the ECC sector D₁[2] using Equation 4:

Q′[2]=g ₀

D ₀[2]⊕g ₂

D ₂[2]⊕g ₃

D ₃[2]⊕ . . . ⊕g _(N−2)

D _(N−2)[2]⊕g _(N−1)

D _(N−1)[2]

D ₁[2]=g ₁ ⁻¹

(Q[2]⊕Q′[2])  (4)

As described above, when a read failure occurs at the third ECC sectorD₁[2] in the second data stripe D₁ and at the third ECC sector P[2] inthe P-parity stripe D_(N), the controller 310 may calculate an ECCsector Q′[2] using Equation 4 and may recover the ECC sector D₁[2] usingthe ECC sector Q′[2] and the decoded ECC sector Q[2]. The controller 310may store the recovered ECC sector D₁[2] in the DRAM 360 and transmit itto the host 200 through the interface 110. Alternatively, the controller310 may generate the ECC sectors P[2] and Q[2] using the recovered ECCsector D₁[2] or Equation 1 and may write the recovered ECC sector D₁[2]and the ECC sectors P[2] and Q[2] to the storage medium 400.

When a read failure occurs in both the ECC sectors D₁[2] and P[2], thecontroller 310 does not read the whole stripe set but reads only the ECCsectors D₀[2], D₂[2] through D_(N−1)[2], and Q[2] included in the thirdcolumn COL2 that includes the ECC sector D₁[2] to recover the ECC sectorD₁[2]. Accordingly, as compared to a conventional data storage devicethat transmits the whole stripe set from a storage medium to acontroller, the amount of data transmitted from the storage medium 400to the controller 310 is reduced.

The operation of the controller 310 that performs the third recoverymode MODE2 when a read failure occurs in two data stripes will bedescribed in detail with reference to FIGS. 1, 2, 6, 9, and 10. It isassumed that a read failure occurs in the ECC sector D₁[j](=D₁[3]=D_(k)[j]) included in the fourth column COL4 of the second datastripe D₁ and in the ECC sector D_(i)[j](=D₂[3]=D_(m)[j]) included inthe fourth column COL4 of the third data stripe D₂. At this time, “i” is1, “k” is 1, “m’ is 2, and “j” is 3. The controller 310 may perform thethird recovery mode MODE2.

When a read failure occurs in the ECC sector D₁[3] in operation S110,the controller 310 provisionally decides to perform the first recoverymode MODE0 in operation S112. Here, c=0 indicates the first recoverymode MODE0.

The controller 310 reads the ECC sector P[j](=P[3]), which is includedin the P-parity stripe D_(N) and placed in the fourth column COL4, fromthe storage medium 400 in operation S114. The ECC encoder/decoder 355may decode the ECC sector P[3]. The decoded ECC sector P[3] may bestored in the DMA controller 345 or the DRAM 360.

The ECC encoder/decoder 355 determines whether the decoded ECC sectorP[3] has an uncorrectable error in operation S116. Because the decodedECC sector P[3] does not have an uncorrectable error, a read failuredoes not occur (which corresponds to a case of NO) in operation S116.

The controller 310 initiates an operation for reading the ECC sectorD₀[3], which is placed in the first row in the fourth column COL4, fromthe storage medium 400 by setting i to 0 in operation S120. BecauseD₀[3] is not D₁[3] (which corresponds to a case of NO) in operationS122, the controller 310 reads the ECC sector D₀[3] from the storagemedium 400 in operation S124. The ECC encoder/decoder 355 may decode theECC sector D₀[3] and store the decoded ECC sector D₀[3] in the DMAcontroller 345 or the DRAM 360.

Because a read failure does not occur with respect to the ECC sectorD₀[3] (which corresponds to a case of NO) in operation S126, thecontroller 310 may perform operation S132. Because D₀[3] is not the ECCsector D_(N−1)[3] included in last data stripe D_(N−1) among the datastripes D₀ through D_(N−1) in operation S132, the controller 310 returnsto the operation S122. The controller 310 initiates an operation forreading the ECC sector D₁[3] placed in the second row in the fourthcolumn COL4 from the storage medium 400 in operation S122. Because D₁[3]is D₁[3] (which corresponds to a case of YES) in operation S122, thecontroller 310 performs operation S132. Because D₁[3] is not the ECCsector D_(N−1)[3] in operation S132, the controller 310 returns to theoperation S122.

The controller 310 initiates an operation for reading the ECC sectorD₂[3], which is placed in the third row in the fourth column COL4, fromthe storage medium 400 in operation S122. Because D₂[3] is not D₁[3](which corresponds to a case of NO) in operation S122, the controller310 performs operation S124. The controller 310 reads the ECC sectorD₂[3] from the storage medium 400 in operation S124. However, becausethe ECC sector D₂[3] has an uncorrectable error, a read failure occurswith respect to the ECC sector D₂[3] (which corresponds to a case of YESin operation S126). The controller 310 performs operation S128. As aresult of performing operation S128, c=2. Because “c” is not greaterthan 2 (which corresponds to a case of NO in operation S130), thecontroller 310 determines whether the ECC sector D₂[3] is the ECC sectorD_(N−1)[3] included in the last data stripe D_(N−1) among the datastripes D₀ through D_(N−1) in operation S132. When “c” is greater than 2(which corresponds to a case of YES in operation S130), the controller310 determines that there is a RAID-6 recovery failure in operationS138.

Because the ECC sector D₂[3] is not the ECC sector D_(N−1)[3] (whichcorresponds to a case of NO in operation S132), the controller 310 readsthe ECC sector D₂[4] from the storage medium 400 in operations S122 andS124. The ECC encoder/decoder 355 may decode the ECC sector D₂[4] andstore the decoded ECC sector D₂[4] in the DMA controller 345 or the DRAM360.

The controller 310 performs operations S122 through S132 on the ECCsectors D₂[3] through D_(N−1)[3]. After operation S126 is performed onthe fourth ECC sector D_(N−1)[3] in the last data stripe D_(N−1) amongthe data stripes D₀ through D_(N−1), the controller 310 determineswhether a current recovery mode is the first recovery mode MODE0 inoperation S134. Because the current recovery mode is the third recoverymode MODE2 (which corresponds to a case of NO in operation S134), thecontroller 310 reads the fourth ECC sector Q[3] in the Q-parity stripeD_(N+1) in operation S136.

The controller 310 determines whether a read failure occurs with respectto the fourth ECC sector Q[3] in operation S140. Because a read failuredoes not occur with respect to the fourth ECC sector Q[3] (whichcorresponds to a case of NO in operation S140), the controller 310determines whether the current recovery mode is the second recovery modeMODE1 in operation S144. Because “c” has been set to 2 in operationS128, the current recovery mode is the third recovery mode MODE2 (whichcorresponds to a case of NO in operation S144). Accordingly, thecontroller 310 performs the third recovery mode MODE2 in operation S148.When a read failure does occur with respect to the fourth ECC sectorQ[3] (which corresponds to a case of YES in operation S140), thecontroller 310 determines that there is a RAID-6 recovery failure inoperation S138.

Because a read failure occurs neither in the fourth ECC sector P[3] inthe P-parity stripe D_(N) nor in the fourth ECC sector Q[3] in theQ-parity stripe D_(N+1) in the third recovery mode MODE2, the controller310 may recover the ECC sectors D₁[3] and D₂[3] using Equation 5:

P′[3]=D ₀[3]⊕D ₃[3]⊕ . . . ⊕D _(N−2)[3]⊕D _(N−1)[3]

Q′[3]=g ₀

D ₀[3]⊕g ₃

D ₃[3]⊕ . . . ⊕g _(N−2)

D _(N−2)[3]⊕g _(N−1)

D _(N−1)[3]

D ₁[3]=(g ₁ ⊕g ₂)⁻¹

(g ₂

(P[3]⊕P′[3])⊕(Q[3]⊕Q′[3]))

D ₂[3]=D ₁[3]⊕(P[3]⊕P′[3])  (5)

As described above, when a read failure occurs at the fourth ECC sectorD₁[3] in the second data stripe D₁ and at the fourth ECC sector D₂[3] inthe third data stripe D₂, the controller 310 may calculate an ECC sectorP′[3] and an ECC sector Q′[3] using Equation 5, may recover the ECCsector D₁[3] using the calculated ECC sectors P′[3] and Q′[3] and thedecoded ECC sectors P[3] and Q[3], and may recover the ECC sector D₂[3]using the calculated ECC sectors P′[3] and Q′[3] and the decoded ECCsectors P[3] and Q[3]. The controller 310 may store the recovered ECCsectors D₁[3] and D₂[3] in the DRAM 360 or the storage medium 400 andtransmit them to the host 200 through the interface 110.

When a read failure occurs in both the ECC sectors D₁[3] and D₂[3], thecontroller 310 does not read the whole stripe set but reads only the ECCsectors D₀[3], D₄[3] through D_(N−1)[3], P[3], and Q[3] included in thefourth column COL4 that includes the ECC sectors D₁[3] and D₂[3] torecover the ECC sectors D₁[3] and D₂[3]. Accordingly, as compared to aconventional data storage device that transmits the whole stripe setfrom a storage medium to a controller, the amount of data transmittedfrom the storage medium 400 to the controller 310 is reduced.

FIG. 11 is a flowchart of an operation of the data storage device 300illustrated in FIG. 1 according to example embodiments. Referring toFIGS. 1 through 11, the controller 310 recovers one ECC sector or twoincluded in one data stripe or two among a plurality of data stripes inoperation S210. It is assumed that one ECC sector or two are recoveredin each of the recovery modes MODE0 through MODE2 described withreference to FIGS. 1 through 10. Accordingly, after all the data stripesare recovered, an ECC sector or ECC sectors included in a P-paritystripe and/or a Q-parity stripe are recovered using Equation 1 inoperation S220.

As described above, according to example embodiments, a data storagedevice having RAID-6 architecture decodes a first data block logicallyor physically placed in a first column among data blocks stored in astorage medium during a read operation, and when a read failure occursin the first data block, the data storage device reads second datablocks logically or physically arranged in the first column except forthe first data block among the data blocks instead of reading all of thedata blocks, and recovers the first data block using the second datablocks. Accordingly, when a read failure occurs in the first data block,the amount of data read from a storage medium is significantly reduced.As a result, the data storage device efficiently recovers data in ashort time. In addition, the data storage device selects the mostefficient mode from a plurality of recovery modes according to thenumber of blocks in which a read failure has occurred among the secondblocks included in the first column, and recovers one data block or twoin which a read failure has occurred using the selected recovery mode.

As is traditional in the field of inventive concepts, exampleembodiments are described, and illustrated in the drawings, in terms offunctional blocks, units and/or modules. Those skilled in the art willappreciate that these blocks, units and/or modules are physicallyimplemented by electronic (or optical) circuits such as logic circuits,discrete components, microprocessors, hard-wired circuits, memoryelements, wiring connections, and the like, which may be formed usingsemiconductor-based fabrication techniques or other manufacturingtechnologies. In the case of the blocks, units and/or modules beingimplemented by microprocessors or similar, they may be programmed usingsoftware (e.g., microcode) to perform various functions discussed hereinand may optionally be driven by firmware and/or software. Alternatively,each block, unit and/or module may be implemented by dedicated hardware,or as a combination of dedicated hardware to perform some functions anda processor (e.g., one or more programmed microprocessors and associatedcircuitry) to perform other functions. Also, each block, unit and/ormodule of the example embodiments may be physically separated into twoor more interacting and discrete blocks, units and/or modules withoutdeparting from the scope of the inventive concepts. Further, the blocks,units and/or modules of the example embodiments may be physicallycombined into more complex blocks, units and/or modules withoutdeparting from the scope of the inventive concepts.

While the inventive concepts have been shown and described withreference to example embodiments thereof, it will be understood by thoseof ordinary skill in the art that various changes in forms and detailsmay be made therein without departing from the spirit and scope of theinventive concepts as defined by the following claims.

1. A data storage device comprising: a storage medium configured tostore data blocks included in a stripe set; and a controller connectedto the storage medium and configured to: decode a first data blockdisposed in a column among the data blocks, during a read operation ofthe first data block; and read first group data blocks disposed in thecolumn among the data blocks, based on a read failure of the first datablock.
 2. The data storage device of claim 1, wherein the stripe set isstored in the storage medium, according to redundant array ofinexpensive/independent disk (RAID)-6.
 3. The data storage device ofclaim 1, wherein the storage medium comprises non-volatile memorydevices, the stripe set comprises data stripes, a P-parity stripe, and aQ-parity stripe, and the data stripes, the P-parity stripe, and theQ-parity stripe are respectively stored in the non-volatile memorydevices.
 4. The data storage device of claim 3, wherein the non-volatilememory devices are respectively included in different ways.
 5. The datastorage device of claim 3, wherein each of the non-volatile memorydevices is a flash memory device, the flash memory device comprises athree-dimensional memory cell array, the three-dimensional memory cellarray comprises memory cells, and each of the memory cells comprises acharge trap layer.
 6. The data storage device of claim 3, wherein thefirst group data blocks comprise: the first data block included in afirst data stripe among the data stripes; a second data block includedin each of second data stripes among the data stripes other than thefirst data stripe; a first P-data block included in the P-parity stripe;and a first Q-data block included in the Q-parity stripe.
 7. The datastorage device of claim 6, wherein the controller is further configuredto read and decode the first P-data block.
 8. The data storage device ofclaim 7, wherein the controller is further configured to: read anddecode the second data block included in each of the second datastripes; and in response a read failure of the first P-data block notoccurring: recover the first data block, using the decoded first P-datablock and the decoded second data block included in each of the seconddata stripes; and transmit the recovered first data block to a host. 9.The data storage device of claim 7, wherein the controller is furtherconfigured to: read and decode the second data block included in each ofthe second data stripes, and the first Q-data block; and based on a readfailure of the first P-data block: generate a second Q-data blockcorresponding to the first Q-data block, using the decoded second datablock included in each of the second data stripes and symbols of aGalois field that correspond to the second data block included in eachof the second data stripes; recover the first data block, using a symbolof the Galois field that corresponds to the first data block, thedecoded first Q-data block, and the second Q-data block; and transmitthe recovered first data block to a host.
 10. The data storage device ofclaim 7, wherein the controller is further configured to: read anddecode the second data block included in each of the second datastripes, and the first Q-data block; and in response to a read failureof the first P-data block not occurring, a read failure of the firstQ-data block not occurring, and a read failure of a third data blockamong the second data blocks occurring: generate a second P-data blockcorresponding to the first P-data block, using decoded fourth datablocks other than the third data block among the decoded second datablock included in each of the second data stripes; generate a secondQ-data block corresponding to the first Q-data block, using the decodedfourth data blocks and symbols of a Galois field that correspond to thedecoded fourth data blocks; recover the first data block, using a firstsymbol of the Galois field that corresponds to the first data block, asecond symbol of the Galois field that corresponds to the third datablock, the decoded first P-data block, the second P-data block, thedecoded first Q-data block, and the second Q-data block; transmit therecovered first data block to a host; recover the third data block,using the recovered first data block, the decoded first P-data block,and the second P-data block; and transmit the recovered third data blockto the host.
 11. A data storage device comprising: a storage mediumconfigured to store data blocks included in a stripe set, according toredundant array of inexpensive/independent disk (RAID) 6; and acontroller connected to the storage medium and configured to: decode afirst data block disposed in a column among the data blocks, during aread operation of the first data block; and read second data blocksdisposed in the column other than the first data block among the datablocks, based on a read failure of the first data block.
 12. The datastorage device of claim 11, wherein the controller is further configuredto: recover the first data block, using the read second data blocks; andtransmit the recovered first data block to a host.
 13. The data storagedevice of claim 11, wherein the controller is further configured to:recover the first data block, using the read second data blocks; andstore the recovered first data block in the storage medium.
 14. The datastorage device of claim 11, wherein the storage medium comprises anon-volatile memory devices, the stripe set comprises data stripes, aP-parity stripe, and a Q-parity stripe, and the data stripes, theP-parity stripe, and the Q-parity stripe are respectively stored in thenon-volatile memory devices.
 15. The data storage device of claim 14,wherein the second data blocks comprise a P-data block included in theP-parity stripe and a Q-data block included in the Q-parity stripe, andthe controller is further configured to read the P-data block.
 16. Thedata storage device of claim 15, wherein the controller is furtherconfigured to: decode the P-data block; and determine whether to readthe Q-data block based on a result of the decoding. 17-20. (canceled)21. A data storage device comprising: a storage medium configured tostore data blocks; and a controller connected to the storage medium andconfigured to: read and decode a first data block disposed in a columnamong the data blocks; read and decode second data blocks disposed inthe column other than the first data block among the data blocks, basedon a read failure of the first data block; and recover the first datablock based on the decoded second data blocks.
 22. The data storagedevice of 21, wherein the second data blocks comprise a first P-datablock and a first Q-data block, and the controller is further configuredto, based on a read failure of the first P-data block: generate a secondQ-data block corresponding to the first Q-data block, based on thirddata blocks other than the first P-data block and the first Q-data blockamong the decoded second data blocks and symbols of a Galois field thatcorrespond to the third data blocks; and recover the first data block,based on a symbol of the Galois field that corresponds to the first datablock, the decoded first Q-data block, and the second Q-data block. 23.The data storage device of 21, wherein the second data blocks comprise afirst P-data block and a first Q-data block, and the controller isfurther configured to, based on a read failure of a third data blockamong the decoded second data blocks: generate a second P-data blockcorresponding to the first P-data block, based on fourth data blocksother than the third data block, the first P-data block, and the firstQ-data block among the decoded second data blocks; generate a secondQ-data block corresponding to the first Q-data block, based on thedecoded fourth data blocks and symbols of a Galois field that correspondto the decoded fourth data blocks; recover the first data block, basedon a first symbol of the Galois field that corresponds to the first datablock, a second symbol of the Galois field that corresponds to the thirddata block, the decoded first P-data block, the second P-data block, thedecoded first Q-data block, and the second Q-data block; and recover thethird data block, based on the recovered first data block, the decodedfirst P-data block, and the second P-data block.